1. Field of Invention
The invention relates to a burst synchronization and error detection device and its method. More particularly, it relates to a burst synchronization and error detection device and the method that is utilized in a communication system (such as the PACS system) using the time-division multiplexing/time division multiplex access (TDM/TDMA) technique.
2. Related Art
In a time-division multiplexing/time division multiplex access (TDM/TDMA) digital communication system, the receiving device is mostly designed with a burst synchronization and error detection device so that when slippage or errors occurs to a burst, the transmitted signal can be synchronized and the errors can be detected.
When the above-mentioned burst synchronization and error detection device performs synchronization and error detection, the cyclic code technique is often used. There is much relevant literature describing such a technique; see, for example, Tavares et. al., xe2x80x9cSynchronization of cyclic codes in the presence of burst errorsxe2x80x9d Information and Control, vol. 14 (1969), PP. 423-441.
Since burst slippage is more serious during the transmission of wireless digital signal, the U.S. Pat. No. 5,084,891 xe2x80x9cTechnique for jointly performing bit synchronization and error detection in a TDM/TDAM systemxe2x80x9d (January 1992) and the R.O.C. Pat. No. 84,113,269 were proposed to solve this problem. As shown in FIG. 1, the synchronization and error detection device of the system disclosed in the above-mentioned U.S. patent contains a synchronization module (loop) 91 and an error detection module 92. The synchronization module 91 and the error detection module 92 generate a tagged bit-sequence using an adder 911, 921 and compute a syndrome using a g (x) divider 912, 922, respectively. As demonstrated in the patent, this can solve the burst slippage problem and detect errors, but the synchronization module 91 and the error detection module 92 need to use a divider to process synchronization and error detection. Therefore, the computation takes longer to complete and the microprocessor in the receiving device spares less time for performing other operations. Similarly, the R.O.C. Pat. No. 84,113,269 has the same problem. Accordingly, how to shorten the processing time of synchronization and error detection so that the processor of the receiving device can have more time to do other operations is a very important subject.
In view of the foregoing, it is a primary object of the invention to provide a burst synchronization and error detection device to more efficiently perform burst synchronization and error detection so as to shorten the processing time.
The invention is characterized in that a syndrome to be shared with the error detection module is generated by the synchronization module of the burst synchronization and error detection device, whereby the syndrome computation time can be reduced in order to shorten the processing time for error detection.
To achieve the above objectives, the burst synchronization and error detection device of the invention comprises a codeword separation module, a message appending module, a first syndrome generating module, a second syndrome generating module, a burst synchronization bit generating module, a tagging module, an error detection slippage module, and an error flag generating module. The codeword separation module receives an n-bit codeword and separates the n-bit codeword into a k-bit (n greater than k) and an (nxe2x88x92k)-bit sequence. The message appending module receives the k-bit sequence output from the codeword separation module and appends (nxe2x88x92k) bits of xe2x80x9c0xe2x80x9d after the k-bit sequence so as to generate an n-bit message appended bit sequence. The first syndrome generating module receives the message appended bit sequence and computes a first syndrome of the message appended bit sequence. The second syndrome generating module generates a second syndrome according to the first syndrome and the (nxe2x88x92k)-bit sequence. The burst synchronization bit generating module outputs a synchronized burst synchronization bit sequence according to the second syndrome. The tagging module receives the synchronization bit sequence and generates a tagged synchronization bit sequence. The error detection slippage module receives the tagged synchronization bit sequence and generates an (nxe2x88x92k)-bit error detection bit sequence for error detection purposes. The error flag generating module generates an error flag value according to the error detection bit sequence and the first syndrome and outputs the error flag value for determining if the received codeword has any error.
Since the first syndrome generated by the first syndrome generating module of the burst synchronization and error detection device can be directly used by the error flag generating module without further calculation, the invention can therefore shorten the error detection processing time.